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Design and Verification

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VLSI (Very Large Scale Integration) RTL (Register Transfer Level) Design and Verification is the process of designing and verifying the functionality of the digital circuits. This process involves implementing circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL Design involves creating a high-level behavioral description of the digital circuit that specifies its functionality, and then translating this description into a register transfer level (RTL) description. The RTL description is a low-level representation of the circuit that specifies the behavior of each individual gate and the connections between them. The RTL description is then used to synthesize the circuit into a gate-level netlist, which can be used to implement the design in hardware.

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Design and Verification Overview

VLSI (Very Large Scale Integration) RTL (Register Transfer Level) Design and Verification is the process of designing and verifying the functionality of the digital circuits. This process involves implementing circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL Design involves creating a high-level behavioral description of the digital circuit that specifies its functionality, and then translating this description into a register transfer level (RTL) description. The RTL description is a low-level representation of the circuit that specifies the behavior of each individual gate and the connections between them. The RTL description is then used to synthesize the circuit into a gate-level netlist, which can be used to implement the design in hardware.

Key Highlights

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Understanding of VLSI Fundamentals
Hands-On Experience with Design Tools
Proficient in RTL Design
Understanding of Synthesis & Optimization
Advanced RTL Design Concepts
Industry Projects and Internships

Who Can Attend?

Any year BTech, MTech, BE, ME pass out students with minimum of 50% in academics are eligible for.

Prerequisites

Any year BTech, MTech, BE, ME pass out students with minimum of 50% in academics are eligible for.

Skills You Will Master

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Physical design and verification engineer

$36999k - $96300k

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Collaborating with World-Class Organizations
Accenture
SAP
Shell
SMBC
WHO
Wincor Nixdorf
Google
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Microsoft
Oracle
IBM
Accenture
SAP
Shell
SMBC
WHO
Wincor Nixdorf
Google
Amazon
Microsoft
Oracle
IBM
Accenture
SAP
Shell
SMBC
WHO
Wincor Nixdorf
Google
Amazon
Microsoft
Oracle
IBM

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The Syllabus

Industry-vetted curriculum designed for 2026 market demands

01

Introduction to VLSI

  • Evolution of VLSI
  • VLSI Design flow cycle
  • Semiconductor Eco-system
  • What is ASIC & FPGA
  • FPGA design flow & ASIC design and verification flow
  • SoC architecture
  • SoC Design flow
  • Opportunities for VLSI engineers in India
  • VLSI industry work profiles and roles
  • How to be industry ready?
02

Digital Design

  • Number Systems and conversions
  • Number System complements (Binary Arithematics - Addition and Subtraction)
  • Boolean algebra, Boolean theorems and laws, Sum of products and product of sums, Minterms and Maxterms
  • Karnaugh map Minimization
  • Logic gates, Enable & disable concept of gates, Tristate logic gates
  • Binary Codes – Binary, BCD, Excess 3, Gray
  • Error detection & correction - Parity method
  • Hazards in combinational circuits
  • Half Adder, Full Adder, RCA
  • Multiplexer, Demultiplexer
  • Encoders, Priority Encoders
  • Decoder (Active high & low outputs), Magnitude Comparator
  • Sequential circuits: Latches (SR Latch, S'R' latch), gated latch (SR, D latch)
  • Clock - Triggering types, clock duty cycle, clock jitter, glitches & skew
  • Sequential circuits: Flipflops & types (characteristic and excitation tables)
  • Master/Slave FF – Operation, timing diagrams
  • Shift registers - SISO, SIPO, PISO, PIPO
  • Shift registers - Universal Shift Register, Bidirectional
  • Design of Counters- Asynchronous Counters - Up, Down, Up-Down counters, Ring Counter, Jhonson counter
  • Synchronous Counters - Up, Down, Up-Down counters
  • Clock generation, Setup time, Hold time, Metastability and frequency calculations, frequency division using counters
  • State Machines Design – Moore models (Overlapping & Non Overlapping)
  • Mealy models (Overlapping & Non Overlapping)
  • Memory structure - ROM/ RAM
  • Synchronous FIFO
  • Asynchronous FIFO
03

Introduction to Linux & Gvim Editor

  • Linux Commands
  • How to work with Gvim Editor Tool
  • Shortcuts & Tricks
04

Verilog HDL

  • Introduction to HDL
  • Differences b/w high level language (C Programming) and HDL, VHDL vs Verilog HDL, VLSI Design Flow cycle.
  • Introducing RTL Design (DUT) and Testbench
  • Defining RTL Design (DUT) and Verilog Testbench, Structure of DUT and Verilog Testbench.
  • What are Ports and types?
  • What is Instantiation?
  • Compilation vs Simulation vs Synthesis
  • Modelling Styles-Levels of Abstraction
  • Data Flow Modelling- Implicit Continuous Assignments
  • Tool Introduction with basic gates or MUX example in Dataflow modelling along with TB
  • Basic Concepts- Lexical Conventions (White Spaces, Comments, Operators, Number Specifications, Strings, Keywords, Identifiers)
  • Data Types (Net Data Types, Register Data Types), System Tasks, Defines, Parameters, timescale
  • Operators (Concatenation, Replication, Negation, Unary Reduction, Arithmetic, Shift, Relational, Equality Logical, Case, Bit-wise, Logical-wise, Conditional)
  • Modelling Styles- Gate Level Modelling- Gate Level Primitives (and, or, nand, nor, xor, xnor, not)
  • Structural Modelling-Instantiation- Naming, Positioning, Example-Ripple Carry Adder
  • Behavioural Modelling- Procedural Blocks- initial and always, Sensitivity list, Blocking assignments/statements
  • Behavioural Modelling- Non-blocking assignments/statements, Inter and Intra Delays
  • Verilog Stratified Queues (Verilog Regions)- Active, Inactive, NBA, Monitor/Postponed Regions
  • Behavioural Modelling- If-else (2x1 and 4x1 Mux), case, casex, casez (4x1 Mux, Priority Encoder)
  • Behavioural Modelling- Looping Statements- for, repeat, while, forever, begin-end, fork-join, naming of blocks, disable
  • Verilog Functions- Introduction, formal arguments, actual arguments, function call, example- Ripple Carry Adder
  • Verilog Tasks- Introduction, example- Ripple Carry Adder, Task based Testbench
  • Verilog Coding- Arrays, Memories (ROM)
  • Verilog Coding- Memories (RAM)
  • Verilog Coding- Finite State Machines (Moore, Mealy -- Overlap, Non-overlap)
  • Verilog Coding- Synchronous FIFO
  • Modelling Styles- Switch Level Modelling- PMOS, NMOS, CMOS- NOT, NAND, NOR, AND, OR Gates (optional)

Your Career Roadmap

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Intensive 3-Month Live Training

Step 1

Topic Wise Interview Questions

Step 2

Scenario Based Learning

Step 3

One - One Sessions

Step 4

Resume Building Sessions

Step 5

Mock Interviews

Step 6

Certification Process

Simple steps journey to your industry-recognized certification.

SkillDeck Certification
Industry Certified
01

Foundational Skills Acquisition

02

Advanced Methodologies

03

EDA Tool Proficiency

04

Project Implementation

Final Assessment

Common Inquiries

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